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LTC1864L/LTC1865L Power, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP
FEATURES

DESCRIPTIO
16-Bit 150ksps ADCs in MSOP Package Single 3V Supply Low Supply Current: 450A (Typ) Auto Shutdown Reduces Supply Current to 10A at 1ksps True Differential Inputs 1-Channel (LTC1864L) or 2-Channel (LTC1865L) Versions SPI/MICROWIRETM Compatible Serial I/O 16-Bit Upgrade to 12-Bit LTC1285/LTC1288 Pin Compatible with 12-Bit LTC1860L/LTC1861L No Minimum Data Transfer Rate
The LTC(R)1864L/LTC1865L are 16-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 3V supply. At 150ksps, the supply current is only 450A. The supply current drops at lower speeds because the LTC1864L/LTC1865L automatically power down between conversions. These 16-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1864L has a differential analog input with an external reference pin. The LTC1865L offers a softwareselectable 2-channel MUX and an external reference pin on the MSOP version. The 3-wire, serial I/O, small MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S

High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition
TYPICAL APPLICATIO
Supply Current vs Sampling Frequency Single 3V Supply, 150ksps, 16-Bit Sampling ADC
1F
SUPPLY CURRENT (A)
1000
CONV LOW = 2s TA = 25C VCC = 2.7V
3V
100
LTC1864L 1 2 ANALOG INPUT 0V TO 3V 3 4 VREF IN + IN - GND VCC SCK SDO CONV 8 7 6 5
1864 TA01
10
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
1
0.1 0.01
0.1 100 1 10 SAMPLING FREQUENCY (kHz)
U
1000
1864L/65L TA02
U
U
sn18645L 18645Lfs
1
LTC1864L/LTC1865L
ABSOLUTE
AXI U
RATI GS
Supply Voltage (VCC) ................................................. 7V Ground Voltage Difference AGND, DGND LTC1865L MSOP Package ......... 0.3V Analog Input ............... (GND - 0.3V) to (VCC + 0.3V) Digital Input ................................ (GND - 0.3V) to 7V Digital Output .............. (GND - 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 400mW
PACKAGE/ORDER I FOR ATIO
TOP VIEW VREF IN + IN GND 1 2 3 4 8 7 6 5 VCC SCK SDO CONV
ORDER PART NUMBER
TOP VIEW
MS8 PACKAGE 8-LEAD PLASTIC MSOP
LTC1864LCMS8 LTC1864LIMS8 LTC1864LACMS8 LTC1864LAIMS8 MS8 PART MARKING LTC7 ORDER PART NUMBER
TJMAX = 150C, JA = 210C/W
TOP VIEW VREF 1 IN + 2 IN - 3 GND 4 8 VCC 7 SCK 6 SDO 5 CONV
LTC1864LCS8 LTC1864LIS8 LTC1864LACS8 LTC1864LAIS8 S8 PART MARKING 1864L 1864LI 1864LA 864LAI
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER A D
PARAMETER Resolution No Missing Codes Resolution INL Transition Noise Gain Error
ULTIPLEXER CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
CONDITIONS

(Note 3)
2
U
U
W
WW U
WU
W
(Notes 1, 2)
Operating Temperature Range LTC1864LC/LTC1865LC/ LTC1864LAC/LTC1865LAC .................... 0C to 70C LTC1864LI/LTC1865LI/ LTC1864LAI/LTC1865LAI ................. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER
CONV CH0 CH1 AGND DGND 1 2 3 4 5 10 9 8 7 6 VREF VCC SCK SDO SDI
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JA = 210C/W
LTC1865LCMS LTC1865LIMS LTC1865LACMS LTC1865LAIMS MS PART MARKING LTJ4 ORDER PART NUMBER
TOP VIEW CONV 1 CH0 2 CH1 3 GND 4 8 VCC 7 SCK 6 SDO 5 SDI
LTC1865LCS8 LTC1865LIS8 LTC1865LACS8 LTC1865LAIS8 S8 PART MARKING 1865L 1865LI 1865LA 865LAI
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
U
LTC1864L/LTC1865L MIN TYP MAX 16 14 8 2
LTC1864LA/LTC1865LA MIN TYP MAX 16 15 6 2 20
UNITS Bits Bits LSB LSBRMS mV

20
sn18645L 18645Lfs
LTC1864L/LTC1865L
CO VERTER A D
PARAMETER Offset Error Input Differential Voltage Range Absolute Input Range VREF Input Range Analog Input Leakage Current CIN Input Capacitance VIN
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
CONDITIONS
DY A IC ACCURACY
TA = 25C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise noted.
SYMBOL PARAMETER SNR THD Signal-to-Noise Ratio 1kHz Input Signal Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal Full Power Bandwidth Full Linear Bandwidth S/(N + D) 75dB S/(N + D) Signal-to-Noise Plus Distortion Ratio CONDITIONS LTC1864L/LTC1865L MIN TYP MAX 82 82 92 10 20 UNITS dB dB dB MHz kHz
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PD High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current (LTC1864L SO-8 and MSOP, LTC1865L MSOP) Supply Current Power Dissipation CONDITION VCC = 3.3V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10A VCC = 2.7V, IO = 360A VCC = 2.7V, IO = 400A CONV = VCC VOUT = 0V VOUT = VCC CONV = VCC fSMPL = fSMPL(MAX) CONV = VCC After Conversion fSMPL = fSMPL(MAX) fSMPL = fSMPL(MAX)
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
LTC1864L/LTC1865L MIN TYP MAX

WU
= IN + (Note 4)
U
WU
U
ULTIPLEXER CHARACTERISTICS
LTC1864L/LTC1865L MIN TYP MAX 2 0 - 0.05 - 0.05 1
LTC1864LA/LTC1865LA MIN TYP MAX 2 0 - 0.05 - 0.05 1 12 5 5 VREF VCC + 0.05 VCC /2 VCC 1
UNITS mV V V V V A pF pF
5 VREF VCC + 0.05 VCC /2 VCC 1
- IN -
IN + Input IN - Input LTC1864L SO-8 and MSOP, LTC1865L MSOP In Sample Mode During Conversion
12 5
UNITS V V A A V V
1.9 0.45 2.5 - 2.5 2.3 2.1 2.6 2.45 0.3 3 - 6.5 6.5
V A mA mA

0.001 0.01 0.5 0.45 1.22
3 0.1 10 1.0
A mA A mA mW
sn18645L 18645Lfs
3
LTC1864L/LTC1865L
RECO
VCC fSCK tCYC tSMPL tsuCONV thDI tsuDI tWHCLK tWLCLK tWHCONV tWLCONV thCONV
full operating temperature range, otherwise specifications are TA = 25C.
SYMBOL PARAMETER Supply Voltage Clock Frequency Total Cycle Time Analog Input Sampling Time (Note 5) Setup Time CONV Before First SCK (See Figure 1) Hold Time SDI After SCK Setup Time SDI Stable Before SCK SCK High Time SCK Low Time CONV High Time Between Data Transfer Cycles CONV Low Time During Data Transfer Hold Time CONV Low After Last SCK LTC1865L LTC1865L fSCK = fSCK(MAX) fSCK = fSCK(MAX) LTC1864L LTC1865L CONDITIONS
E DED OPERATI G CO DITIO S
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL tCONV tdDO tdis ten thDO tr tf PARAMETER Conversion Time (See Figure 1) Delay Time, SCK to SDO Data Valid Delay Time, CONV to SDO Hi-Z Delay Time, CONV to SDO Enabled Time Output Data Remains Valid After SCK SDO Rise Time SDO Fall Time CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CONDITIONS

TI I G CHARACTERISTICS
fSMPL(MAX) Maximum Sampling Frequency
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Assumes fSCK = fSCK(MAX) In the case of the LTC1864L SCK does not have to be clocked during this time if the SDO data word is not desired. In the case of the LTC1865L a minimum of 2 clocks are required on the SCK input after CONV falls to configure the MUX during this time.
4
U
U
U
U WW
The denotes specifications which apply over the
LTC1864L/LTC1865L MIN TYP MAX 2.7
UNITS V MHz s SCK SCK ns ns ns 1/fSCK 1/fSCK s SCK ns
3.6 8
DC 16 * SCK + tCONV 16 14 60 30 30 45% 45% tCONV 16 26
UW
LTC1864L/LTC1865L MIN TYP MAX 3.7 150 45 55 35 5 15 25 12 55 60 120 120 4.66
UNITS s kHz ns ns ns ns ns ns ns
sn18645L 18645Lfs
LTC1864L/LTC1865L TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling Frequency
1000 CONV LOW = 2s TA = 25C VCC = 2.7V 600 500 fS = 150kHz VCC = 2.7V VREF = 2.5V
SHUTDOWN CURRENT (A)
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
100
10
1
0.1 0.01
0.1 100 1 10 SAMPLING FREQUENCY (kHz)
Reference Current vs Sampling Rate
10 9 CONV LOW = 2s TA = 25C VCC = 2.7V VREF = 2.5V 25
REFERENCE CURRENT (A)
REFERENCE CURRENT (A)
7 6 5 4 3 2 1 0 0 25 75 100 125 50 SAMPLING FREQUENCY (kHz) 150
15
REFERENCE CURRENT (A)
8
Typical INL Curve
4 VCC = 2.7V VREF = 2.5V fS = 150kHz 2 1 2
ANALOG INPUT LEAKAGE (nA)
DNL ERROR (LSBs)
INL ERROR (LSBs)
0
-2
-4
0
16384
32768 CODE
49152
UW
1864L/65L G01 1864L/65L G04 1865 G02
Supply Current vs Temperature
20
Sleep Current vs Temperature
fS = 150kHz VCC = 2.7V VREF = 2.5V
15
400 300 200 100 0 -50 -25
10
5
1000
50 25 75 0 TEMPERATURE (C)
100
125
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
1864L/65L G02
1864L/65L G03
Reference Current vs Temperature
25 fS = 150kHz VCC = 2.7V VREF = 2.5V
Reference Current vs Reference Voltage
fS = 150kHz TA = 25C VCC = 3.6V
20
20
15
10
10
5
5
0 -50 -25
0 50 25 75 0 TEMPERATURE (C) 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 REFERENCE VOLTAGE (V) 3.5 4.0
1864L/65L G05
1864L/65L G06
Typical DNL Curve
100 VCC = 2.7V VREF = 2.5V fS = 150kHz
Analog Input Leakage Current vs Temperature
CONV = 0V VCC = 2.7V VREF = 2.5V
75
0
50
-1
25
65536
-2
0
16384
32768 CODE
49152
65536
1865 G03
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
1864L/65L G09
sn18645L 18645Lfs
5
LTC1864L/LTC1865L TYPICAL PERFOR A CE CHARACTERISTICS
Change in Offset vs Reference Voltage
20 15
CHANGE IN OFFSET (LSB)
GHANGE IN GAIN ERROR (LSB)
fS = 150kHz TA = 25C VCC = 3.6V
CHANGE IN OFFSET (LSB)
10 5 0 -5 -10 -15 -20 0 2 3 1 REFERENCE VOLTAGE (V) 4
1864L/65L G10
Change in Gain Error vs Temperature
5 4
CHANGE IN GAIN ERROR (LSB)
VCC = 2.7V VREF = 2.5V
3 2
800
FREQUENCY
1 0 -1 -2 -3 -4 -5 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125
648 600 400 200 0 407
689 576
291 169 52 152
45 20 07 00 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CODE
1864L/65L G14
AMPLITUDE (dB)
SINAD vs Input Frequency
100 90 80 70
SINAD (dB) THD (dB)
50 40 30 20 10 0 1 fS = 125kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V 10 INPUT FREQUENCY (kHz) 100
1864L/65L G16
-50 -60 -70 -80 -90
SFDR (dB)
60
SINAD
6
UW
1864L/65L G13
Change in Offset vs Temperature
5 4 3 2 1 0 -1 -2 -3 -4 -5 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125 VCC = 2.7V VREF = 2.5V 5 4 3 2 1 0 -1 -2 -3 -4 -5
Change in Gain Error vs Reference Voltage
fS = 150kHz TA = 25C VCC = 3.6V
0
2 3 1 REFERENCE VOLTAGE (V)
4
1864L/65L G12
1864L/65L G11
Histogram of 4096 Conversions of a DC Input Voltage
1200 1040 1000 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
4096 Point FFT Nonaveraged
fS = 125kHz TA = 25C VCC = 3V VIN = 0.946045kHz VREF = 3V
0
5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT FREQUENCY (kHz)
1864L/65L G15
THD vs Input Frequency
0 SNR -10 -20 -30 -40 fS = 125kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V 100 90 80 70 60 50 40 30 20 10 1 10 INPUT FREQUENCY (kHz) 100
1864L/65L G17
SFDR vs Input Frequency
-100
fS = 125kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V 1 10 INPUT FREQUENCY (kHz) 100
1864L/65L G18
0
sn18645L 18645Lfs
LTC1864L/LTC1865L
PI FU CTIO S
LTC1864L VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. IN +, IN- (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers LTC1865L (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. LTC1865L (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin.
sn18645L 18645Lfs
U
U
U
down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND.
7
LTC1864L/LTC1865L
FUNCTIONAL BLOCK DIAGRA
PIN NAMES IN PARENTHESES REFER TO LTC1865L
CONVERT CLK
IN (CH0)
+
IN - (CH1)
GND
TEST CIRCUITS
Load Circuit for t dDO, t r, t f, t dis and t en
TEST POINT
3k SDO 20pF
VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1
1864 TC01
Voltage Waveforms for t en
CONV
CONV
SDO ten
1864 TC03
Voltage Waveforms for SDO Delay Times, t dDO and t hDO
SCK VIL tdDO thDO VOH SDO VOL
1864 TC02
8
W
VCC CONV (SDI) SCK BIAS AND SHUTDOWN DATA IN 16 BITS SERIAL PORT SDO
U
U
+ -
16-BIT SAMPLING ADC
DATA OUT
1864/65 BD
VREF
Voltage Waveforms for SDO Rise and Fall Times, t r, t f
VOH VOL tr tf
SDO
1864 TC04
Voltage Waveforms for t dis
VIH
SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2)
90%
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1864 TC05
sn18645L 18645Lfs
LTC1864L/LTC1865L
APPLICATIO S I FOR ATIO
LTC1864L OPERATION Operating Sequence
The LTC1864L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1864L goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1864L goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1.
CONV tCONV SLEEP MODE 1 SCK DON'T CARE 2 3 4 5 6 7
SDO Hi-Z
Figure 1. LTC1864L Operating Sequence
1F VCC
1111111111111111 1111111111111110
* * *
0000000000000001 0000000000000000 VIN*
*VIN
= IN + - IN -
Figure 2. LTC1864L Transfer Curve
U
Analog Inputs The LTC1864L has a unipolar differential analog input. The converter will measure the voltage between the "IN + " and "IN - " inputs. A zero code will occur when IN+ minus IN - equals zero. Full scale occurs when IN+ minus IN - equals VREF minus 1LSB. See Figure 2. Both the "IN+ " and "IN - " inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If "IN - " is grounded and VREF is tied to VCC, a rail-to-rail input span will result on "IN+ " as shown in Figure 3. Reference Input The voltage on the reference input of the LTC1864L defines the full-scale range of the A/D converter. The LTC1864L can operate with reference voltages from VCC to 1V.
t SMPL 8 9 10 11 12 13 14 15 16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1854 F01
W
UU
0V 1LSB
LTC1864L 1 VIN = 0V TO VCC 2 3 4
VREF VREF - 1LSB VREF - 2LSB
VREF IN + IN - GND
VCC SCK SDO CONV
8 7 6 5
1864 F03
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
1864 F02
Figure 3. LTC1864L with Rail-to-Rail Input Span
sn18645L 18645Lfs
9
LTC1864L/LTC1865L
APPLICATIO S I FOR ATIO
LTC1865L OPERATION Operating Sequence The LTC1865L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1865L goes into sleep mode drawing only leakage current. The LTC1865L's 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the "+" and "-" signs in the selected row of Table 1. In
SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE
CONV tCONV SLEEP MODE
SDI
DON'T CARE
SCK
DON'T CARE
SDO
Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Figure 4. LTC1865L Operating Sequence
10
U
single-ended mode, all input channels are measured with respect to GND. A zero code will occur when the "+" input minus the "-" input equals zero. Full scale occurs when the "+" input minus the "-" input equals VREF minus 1LSB. See Figure 5. Both the "+" and "-" inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the "-" input in differential mode is grounded, a rail-to-rail input span will result on the "+" input. Reference Input The reference input of the LTC1865L SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1865L MSOP package defines the span of the A/D converter. The LTC1865L MSOP package can operate with reference voltages from 1V to VCC.
Table 1. Multiplexer Channel Selection
MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + - - + GND - -
1864 TBL1
W
UU
t SMPL
S/D O/S 1 2 3 4 5 6 7
DON'T CARE 8 9 10 11 12 13 14 15 16
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
1864 F04
sn18645L 18645Lfs
LTC1864L/LTC1865L
APPLICATIO S I FOR ATIO
GENERAL ANALOG CONSIDERATIONS Grounding
The LTC1864L/LTC1865L should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1865L MSOP package and GND for the LTC1864L and LTC1865L SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can
1111111111111111 1111111111111110
* * *
0000000000000001 0000000000000000 VIN*
*VIN = (SELECTED "+" CHANNEL) - (SELECTED "-" CHANNEL) REFER TO TABLE 1
Figure 5. LTC1865L Transfer Curve
U
induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1F tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1864L/ LTC1865L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200 or high speed op amps are used (e.g., the LT(R)1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins.
1LSB VCC VCC - 1LSB VCC - 2LSB
1864 F05
W
UU
0V
sn18645L 18645Lfs
11
C3 10F 6.3V 1206 C4 0.1F RN1 330
3
+
2 3 C8 470pF 1205 U3 LTC1864LAIMS8 C21 47pF U8A 74AC14 1 V 2 REF +IN 3 -IN 4 GND 8 VCC 7 SCLK 6 DOUT 5 CONV 1 2 3 4 8 7 6 5 R5 402 1%
7
LTC1864L/LTC1865L
E8 C7 100pF 1206
AGND
2
U2 OPT
6
R1 100 1206
-
E9
J2 1
C6 -15V 0.1F
ON
APPLICATIO S I FOR ATIO
IN - C9 100pF 1206 R6 402 1% C22 47pF U8B 74AC14
IN -
BUF OFF JP2 R2 100
5632
3
IN-
-IN GND JP3
ANALOG GROUND PLANE
16 15 14 13 12 11 10 9
QB VCC QC QA QD A QE OENB QF LCLK QG SCLK QH RESET GND SQH U5 74HC595ADT
1 2 3 4 5 6 7 8
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 U4 3.3VDIG 74HC595ADT 16 QB V 15 CC QC QA 14 QD A 13 QE OENB 12 QF LCLK 11 QG SCLK 10 RESET QH 9 GND SQH 1 2 3 4 5 6 7 8
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
3.3VDIG 3.3VDIG
C23 0.1F C24 0.1F
C15 3.3VDIG 0.1F U9C 74AC00 U9D 74AC00
U9B 74AC00
U12A 74AC109 16 2 6 VCC Q J 3 7 Q K 4 CLK 1 CLR 5 8 GND PRE U12B 74AC109 16 JP4 14 10 VCC CONV Q J 3 13 91 Q K 12 2 EXT INT CLK 15 CLR 11 8 PRE GND 3.3VDIG 3.3VDIG C17 0.1F C16 0.1F 3.3VDIG
C10 3.3VDIG 0.1F
E2
CONV
U9A 74AC00
1 U8D 74AC14 U8E 74AC14 GND U8F 74AC14
2
3 EN EXT JP5
E3 ENABLE DATA E7 DGND E6 E4 E5 DGND DOUT
3.3VDIG U7 74HC163AD R7 20k 3.3VDIG
P0
3.3VDIG
P0
2
4
6
U6 74HC163AD
C18 0.1F CKIN 1 OUT DIV 5 1+ V 2 GND 3 SET 4 3 INT JP6 CLK 1 2 EXT CKIN 3 2 JP7 EXTCK
CLKOUT J3 CLKIN U10 LTC1799 C19 3.3VDIG 0.1F R9 51 2365
JP8
P1 R8 1M
1
3
5
P1
P2
P2
2
4
6
1 2 3 4 5 6 7 8 VCC RCO Q0 Q1 Q2 Q3 ENT LO VCC RCO Q0 Q1 Q2 Q3 ENT LO R10 10k 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND 16 15 14 13 12 11 10 9
JP9
RESET CLK P0 P1 P2 P3 ENP GND
U8C 74AC14
U13A 74AC32
U13D 74AC32
P3 CLK U13B 74AC32 U13C 74AC32 NOTES: UNLESS OTHERWISE SPECIFIED INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2; ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
1864/65 AI1
1
3
5
sn18645L 18645Lfs
P3
U
2
W
4
1
UU
12
LTC1864L Evaluation Circuit Schematic
15V R4 2 C13 0.1F C14 0.1F J4 3201S40G1 C12 10F 6.3V 1206 6 C1 0.1F 3 BUF C2 1F 10V 0805 3.3VAN R3 2 1 LT1121-3.3 3 VIN VOUT GND 2 3.3VAN 3.3VDIG 3.3VDIG 3.3VDIG JP1 +IN
E1
15V
U1 LT1460DCS8-2.5
15V
2
VIN
C20 0.1F
VOUT GND 4
J1
IN +
IN +
1
5632
C5 15V 0.1F
IN+
LTC1864L/LTC1865L
APPLICATIO S I FOR ATIO
Component Side Silk Screen for LTC1864L Evaluation Circuit
Component Side Showing Traces (Note Wider Traces on Analog Side)
Ground Layer with Separate Analog and Digital Grounds
U
Bottom Side Showing Traces (Note Almost No Analog Traces on Board Bottom) Supply Layer with 5V Digital Supply and Analog Ground Repeated
sn18645L 18645Lfs
W
UU
13
LTC1864L/LTC1865L
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.42 0.04 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT
DETAIL "A" 0 - 6 TYP
4.90 0.15 (1.93 .006)
0.254 (.010) GAUGE PLANE
0.18 (.077) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.13 0.076 (.005 .003)
MSOP (MS8) 0802
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
14
U
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.2 - 3.45 (.126 - .136) 0.65 (.0256) BSC
3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.206) REF 3.00 0.102 (.118 .004) NOTE 4
1 23 4
0.53 0.015 (.021 .006) DETAIL "A"
1.10 (.043) MAX
0.86 (.034) REF
0.65 (.0256) BSC
sn18645L 18645Lfs
LTC1864L/LTC1865L
PACKAGE DESCRIPTIO
.050 BSC
8
.245 MIN
.030 .005 TYP
RECOMMENDED SOLDER PAD LAYOUT .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 0- 8 TYP
NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
GAUGE PLANE 12345 0.53 0.01 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.13 0.076 (.005 .003)
MSOP (MS) 0802
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 - .197 (4.801 - 5.004) NOTE 3 7 6 5
.045 .005
.160 .005 .228 - .244 (5.791 - 6.197)
.150 - .157 (3.810 - 3.988) NOTE 3
1
2
3
4
.053 - .069 (1.346 - 1.752)
.004 - .010 (0.101 - 0.254)
.016 - .050 (0.406 - 1.270)
.014 - .019 (0.355 - 0.483) TYP
.050 (1.270) BSC
SO8 0303
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005)
3.2 - 3.45 (.126 - .136)
3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6
0.497 0.076 (.0196 .003) REF
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.15 (1.93 .006)
3.00 0.102 (.118 .004) NOTE 4
1.10 (.043) MAX
0.86 (.034) REF
0.50 (.0197) BSC
sn18645L 18645Lfs
15
LTC1864L/LTC1865L
TYPICAL APPLICATIO
AGND 1F
RELATED PARTS
PART NUMBER 12-Bit Serial I/O ADCs LTC1860L/LTC1861L LTC1860/LTC1861 14-Bit Serial I/O ADCs LTC1417 LTC1418 16-Bit Serial I/O ADCs LTC1609 LTC1864/LTC1865 References LT1460 LT1790 Op Amps LT1468/LT1469 LT1806/LT1807 LT1809/LT1810 Single/Dual 90MHz, 16-Bit Accurate Op Amps Single/Dual 325MHz Low Noise Op Amps Single/Dual 180MHz Low Distortion Op Amps 22V/s Slew Rate, 75V/125V Offset 140V/s Slew Rate, 3.5nV/Hz Noise, - 80dBc Distortion 350V/s Slew Rate, - 90dBc Distortion at 5MHz Micropower Precision Series Reference Micropower Low Dropout Reference Bandgap, 130A Supply Current, 10ppm/C, Available in SOT-23 60A Supply Current, 10ppm/C, SOT-23 200ksps 250ksps 65mW 4.25mW Configurable Bipolar or Unipolar Input Ranges, 5V MSOP, SO-8, 1- and 2-Channel, 5V Supply 400ksps 200ksps 20mW 15mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or 5V Serial/Parallel I/O, Internal Reference, 5V or 5V 150ksps 250ksps 1.22mW 4.25mW Pin Compatible with LTC1864L/LTC1865L Pin Compatible with LTC1864/LTC1865 SAMPLE RATE POWER DISSIPATION DESCRIPTION
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
U
Tiny 2-Chip Data Acquisition System
1F 3V 0.1F 8 3V
+
VIN 3 LTC6910-1
4 5
VREF 1 499 270pF
VCC
-
2
7
6
IN+ SCK LTC1864L SDO IN - GND CONV
ADC GAIN CONTROL CONTROL LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN RANGE TO THE LTC1864L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY
1864L/65L TA03
sn18645L 18645Lfs LT/TP 0403 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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